Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor
Pat Conway, Nathan Kalyanasundharam, Gregg Donley, Kevin M. Lepak, Bill Hughes · IEEE Micro · 2010
The 12-core AMD Opteron processor, code-named "Magny Cours," combines advances in silicon, packaging, interconnect, cache coherence protocol, and server architecture to increase the compute density of high-volume commodity 2P/4P blade servers while operating within the same power envelope as earlier-generation AMD Opteron processors. A key enabling feature, the probe filter, reduces both the bandwidth overhead of traditional broadcast-based coherence and memory latency.