Process‐graph analyser: A front‐end tool for VHDL behavioural synthesis
J. Bhasker · Software Practice and Experience · 1988
Abstract A front‐end of an electronic CAD synthesis system is described. The synthesis system accepts a behavioural description of a digital system design written in VHSIC Hardware Description Language (VHDL) and produces the physical hardware, at the register transfer level, needed for realizing the specified behaviour. The synthesis system comprises three major subsystems: process‐graph analyser, design representation and the MIMOLA synthesis system. The process‐graph analyser is an optimization and parallelization tool. We show how optimizing techniques used for compilers are adapted to perform a similar optimization function for hardware synthesis. We present techniques that extend the parallelization of the sequential programs concept for doing control state partitioning. The technique is new because of the unique synthesis model that MIMOLA uses. Finally, we show how to integrate these concepts using a suitable intermediate behavioural representation called the process graph.