Design of a GALS-NoC Using Soft-cores on FPGAs
Katabami Hideki, Hiroshi Saito, Tomohiro Yoneda · 2013
In this paper, we propose a Globally-Asynchronous Locally-Synchronous Network-on-Chip (GALS-NoC) architecture for FPGAs. Each node in the proposed GALS-NoC is based on a soft-core processor for FPGAs. Each node also has a local clock generator with a clock gating circuit to reduce power consumption of nodes. The asynchronous network in the proposed GALS-NoC is based on MouseTrap. In addition to the proposed GALS-NoC, we propose three functions which control data transfers and distribution of local clock signal at application level. Moreover, we propose a design method for the proposed GALS-NoC using a design support tool set for FPGAs. In the experiments, we evaluate the execution time, power consumption, and energy consumption of the proposed GALS-NoC comparing with a single-clock NoC and a multi-clock NoC.