CBX-1 Switch: An Effective Load Balanced Switch
Xiaoliang Wang, Xiaohong Jiang, Susumu Horiguchi · 2007
Load balance (LB) switch architecture is attractive for building high speed switches since it does not require a centralized scheduler and still can guarantee 100% throughput under any admissible traffic. It is notable, however, that due to the multi-path property of LB switches, the packet out-of-sequence problem may happen in such switches. Several schemes have been proposed to tackle the above problem, but these schemes either require infinite central buffer or introduce a high average packet delay. In this paper, we propose a new LB switch architecture - central buffer one-packet-crosspoint (CBX-1). The key idea ofCBX-1 is to introduce a VIOQ (virtual input output queue) with capacity one (i.e., it can store only one packet) after the first stage of a LB switch to emulate a CIXB-1 switch (combined input-one-packet-crosspoint buffered switch). We show through both analysis and simulation that although our architecture requires only finite central buffer to tackle the packet out-of-sequence problem, it still guarantees 100% throughput and achieves a good delay performance.