A fully pipelined, high speed DFT architecture
F. Kocsis · 1991
A one-dimensional fully pipelined architecture for evaluating the discrete Fourier transform (DFT) is presented. The computational algorithm is based on a modified Horner's rule and can be easily mapped into a binary tree structure. It does not require data reorderings during the computations. As processing elements, optimized CORDIC units are proposed. The DFT processor works in block mode and consists of N processing elements. The time needed to produce a complete N-point transform equals the time of N elementary computing steps. The initial delay is proportional to log/sub 2/ N. The signal-to-noise ratio is similar to that of the FFT algorithm. All the required communications are local, and the dataflow is unidirectional. As the necessary rotations are known in advance and fixed, the hardware complexity of the CORDIC elements can be minimized.>