Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations
Chun-Hsiung Hung, Meng‐Fan Chang, Yih-Shan Yang, Yao‐Jen Kuo, Tzu-Neng Lai, Shin-Jang Shen, Jo-Yu Hsu, Shuo-Nan Hung, Hang-Ting Lue, Yen-Hao Shih, Shih-Lin Huang, Ti-Wen Chen, Tzung Shen Chen, Chung Kuang Chen, Chi-Yu Hung, Chih-Yuan Lu · IEEE Journal of Solid-State Circuits · 2015
3D vertical-gate (3DVG) NAND flash is a promising candidate for next-generation high-density nonvolatile memory. Cross-layer process variation renders 3DVG NAND susceptible to decreased speeds, yield, and reliability. This can be attributed to (a) cross-layer mismatch in bitline capacitance ($C _{BL}$), (b) the need for long program cycles, and (c) sensing-margin (SM) loss induced by the effects of background-pattern-dependency (BPD). This study proposes three circuit-level techniques to overcome these issues by employing the following: (1) distributed NAND-string scramble (DNSS), (2) layer-aware program-verify-and-read (LA-PV-R), and (3) a layer-aware-bitline-precharge (LA-BP) scheme. For an 8-layer 3DVG with 200 mV cross-layer mismatch in cell threshold voltage ($V _{THC}$), DNSS reduces the cross-layer$C _{BL}$-mismatch by 41%, LA-PV-R using various program-threshold-voltages ($V _{THP}$) for each layer enables a 25% reduction in the number of program cycles, and LA-BP succeeds in reducing BPD-induced SM loss by 56%. A 2-layer 3DVG NAND testchip and 8-layer testkey were fabricated to evaluate the proposed methods. The LA-PV-R and LA-BP have achieved a 0.75 V difference in$V _{THP}$between layer-0 and layer-1 with a 0.4V difference in BL clamping bias voltages and the LA-BP scheme has achieved a 44% reduction in BPD-induced SM loss. The three proposed schemes incur an area penalty of less than 0.1% in a Gb-scale 3DVG NAND device.