An On-chip Heterogeneous Implementation of a General Sparse Linear Solver
Arash Sadrieh, Stefano Charissis, Adam Parker Hill · 2013
Inter-device communication is a common limitation of GPGPU computing methods. The on-chip heterogeneous architecture of a recent class of accelerated processing units (APUs), that combine programmable CPU and GPU cores on the same die, presents an opportunity to address this problem. Here we describe an APU-based heterogeneous implementation of the Jacobi-preconditioned conjugate gradient method and identify a set of optimal configurations based on examination of standard matrices. By leveraging the low-latency memory transactions of the APU and exploiting CPU/GPU cohabitation for concurrent vector operations, a comparable performance to that of a high-end GPU running CUSP is achieved. Our results show that use of on-chip heterogeneous architectures can be attractively cost-effective and even show better performance for applications with a low number of linear solver iterations and when device-to-device data transfer is significant. Accordingly, the APU architecture and associated GPAPU methods have significant potential as a low cost, energy efficient alternative for parallel HPC architectures.