A CMOS 32b single chip microprocessor
Bernard T. Murphy, R. Edwards, Lee C. Thomas, John J. Molinelli · 1981
A FULL 32b CPl* implemented in CMOS using a latc.h-up free twin-tub technology will be described, citing the architecture from both the user's external and internal hardware viewpoints. From the user's viewpoint the CPU supports efficient compi lation of high level languages with respect to both code space and execution time. In addition, it has features which support the design of an operating system. The instruction set is orthogonal so that any opcode can be nsed with any operand descriptor. Some instructions handle bit fields and blocks as well. The addressing modes are quite extensive and arc indicated in Table l. The instruction set is very effective at data manipulation.