VLSI design of clustering analyser using systolic arrays
M.F. Lai, Masahiko Nakano, Yebo Wu, Chaur‐Heh Hsieh · IEE Proceedings - Computers and Digital Techniques · 1995
Presents a VLSI architecture for clustering analysers. The proposed VLSI architecture exploits two-dimensional systolic arrays, which use a high degree of parallel and pipelined processing. The architecture dramatically reduces the immense number of processing elements which were required by previous architectures. Moreover, the same architecture can be utilised for applications with a variable number of input patterns. Also, unlike previous architectures, the patterns are applied to the inputs in a serial format, which can save a large number of pin counts, and therefore the proposed architecture is very attractive for VLSI implementation. Using the proposed architecture, the complexity of the VLSI circuit of the clustering analyser can be reduced significantly.