Design and VLSI implementation of an address generation coprocessor
Paul T. Hulina, Lee D. Coraor, L. Kurian, Eugene B John · IEE Proceedings - Computers and Digital Techniques · 1995
Most applications of general purpose VLSI processors are developed using high level languages. In these languages, information is generally handled in a structured form. Compilers generate a considerable amount of code to navigate through the data structures and considerable processing time is spent performing address calculations required to access the data structures. An alternative to software address generation, a hardware memory reconfiguring unit or an address generation coprocessor is presented. To demonstrate the VLSI feasibility of the designed device, it is implemented in VLSI using the Octtool suite of tools. The tools used and the implementation procedure are described. VLSI design aspects such as regularity, modularity, scalability, etc. are discussed. The performance of the device is evaluated using assembly language programs that implement popular signal processing algorithms such as convolution, correlation, FFT and matrix multiplication. A system with the address generation unit exhibits a speed up of between approximately 1.5 and 2.5.