A multiprocessor memory interface simulator
D. S. Taylor, Thomas G. Williams, James E Weatherbee · ACM SIGSIM Simulation Digest · 1974
A simulater is described which models the interference produced at the interface between a common central memory (CM) and a number of microprogrammed central processing units (CPU's) operating under the control of a microprogram read-only memory (MROM).Results of the interference study may be used to determine the optimum combination of the CM/ CPU bus width and the CPU Microprogram MROM cycle time.