Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL
Fareena Saqib, Dylan Ismari, Charles Lamech, Jim Plusquellic · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2014
Variations in path delays are increasing with scaling, and are increasingly affected by neighborhood interactions. To fully characterize within-die variations, delays must be measured in the context of actual core-logic macros using embedded test structures (ETSs). In this brief, we propose an ETS called regional delay behavior (REBEL) that is designed to measure path delays in a minimally invasive fashion. REBEL provides capabilities similar to an off-chip logic analyzer. We implemented REBEL in a 90-nm test chip and present results on within-die path delay variations in a floating point unit. We also analyze the impact on delay when the chips are subjected to industrial-level temperature and voltage variations.