An Improved VLSI ImplementationMethod of FFT Processor
Guihua Liu, Quanyuan Feng · 2006
An improved VLSI realization of a 1024-dot pipeline FFT processor for handling high speed digital signal has been presented by optimizing the pipeline of complex multiplication and the generation of twiddle factor, The method based on CORDIC algorithm is adopted to achieve a real-time FFT processor and results in a substantial savings in hardware resources and the amount of delay elements. It is easily implemented in hardware. The processor has been successfully applied to a Xilinx Virtex- IIxc2v500 chip and obtains the operating clock frequency at 132 MHz