A digital signal processor for telecommunications applications
James R. Boddie, G. T. Daryanani, I. I. Eldumiati, Renato N. Gadenz, JOHN S. JUN. THOMPSON, Steve Walters, R. Pedersen · 1980
This paper will report on a programmable digital signal processor chip which can decode on instruction, fetch data, perform a 16 × 20b multiply, and add the resultant to a 40b accumulator in 80ns. Circuit permits all signal processing functions of a dual-tone multifrequency receiver or a low-speed modem to be realized on one chip.