Efficient implementation of Low Density Parity Check codes for satellite ground terminals
Nareder Kumar, Chandra Prakash, S N Satashia, Virender Kumar, K.S. Parikh · 2014
Low Density Parity Check (LDPC) codes have gained lot of importance in the channel coding arena, because these can provide excellent performance close to Shannon limit & can easily beat the best known turbo codes for large block lengths. This paper explains generic algorithms for hardware efficient implementation of Encoder & Decoder for LDPC codes adopted by Digital Video Broadcast-Satellite-Second Generation (DVB-S2) standard. Low complexity & high throughput architectures have been proposed for LDPC Encoder & Sum Product Algorithm based LDPC Decoder. MATLAB & HDL simulation results are presented for proposed encoder & decoder architectures. Satellite link test results of a scaled down FPGA based implementation with IESS satellite modem are also presented.