Simplifying FPGA design with a novel network-on-chip architecture
John Malsbury, Matt Ettus · 2013
As wireless communications continue to evolve, complex new standards force researchers to adopt heterogeneous design approaches that include general purpose processors (GPP) and field-programmable gate arrays (FPGA). This combination leads to increased processing throughput, decreased latency, and increased development complexity. Compared to GPP implementations, custom FPGA designs are time-consuming. The Third-Generation Ettus Research USRPTM (Universal Software Radio Peripheral) has been developed with a unique processing and routing architecture based on VITA-49, which can drastically reduce FPGA development time. This architecture allows users to easily integrate custom IP, such as channelizes, modulators, demodulators, processors or protocol stacks. The architecture will also permit scalable designs that can distribute processing across many nodes. This paper will examine this architecture and how it will reduce development time for researchers. A practical example will also be provided for reference.