Helping in a multiprocessor environment
Michael Hohmuth, Michael Peter · 2001
This report presents Fiasco-SMP, a port of the Fiasco microkernel to the multiprocessor-x86 architecture. We the discuss design principles we used, and the resulting design for remote-thread manipulation in Fiasco. In particular, we show how we extended Fiasco's implementation of priority inheritance to fit a multiprocessor environment. Our design has two desirable properties. First, it minimizes the number of inter-processor interrupts (IPIs) in the system. Second, for the normal (uncontented) case, it avoids synchronous inter-processor notifications (where one CPU needs to wait for the result of an IPI it sent to another CPU), thereby removing the effect of IPI latency on CPU-local execution---even when manipulating remote threads. Moreover, we propose an extension to the L4 interface that allows server threads to specify that the kernel is allowed to schedule them on a remote CPU (i. e., not on their home CPU) when they become runnable after an IPC. We believe that this behavior h...