A highly-parallel single-chip DSP architecture for video signal processing
H. Yamauchi, Y. Tashiro, Taichi Minami, Y. Suzuki · 1991
The architecture of a newly developed highly parallel pipeline DSP that achieves over 300 MOPS/LSI programming capability is presented. This programmable single-chip DSP is designed for application to a variety of different single-board moving image codecs, which require a DSP with roughly 10 times the power of conventional single pipeline unit architecture DSPs. Assuming 0.8- mu m CMOS technology, a single-chip DSP architecture integrating four sets of pipeline processing units was extensively studied. The DSP configuration and noble techniques enabling efficient operation of plural pipeline processing units are described. Evaluation of the performance of the DSP is also presented.>