ProperSYN: a portable parallel algorithm for logic synthesis
K. De, Balkrishna Ramkumar, Prithviraj Banerjee · 1992
Parallel processing is fast becoming an attractive solution to reduce the computation time of CAD applications. Much of the work in parallel algorithms for CAD reported to date, however, suffers from a major limitation. The parallel algorithms proposed for the CAD applications are designed with a specific underlying parallel architecture in mind. We have developed a portable parallel algorithm based on the Transduction method [1], called ProperSYN. The same algorithm runs on a variety of parallel machines. Experimental results on various parallel machines are presented. 1 Introduction Combinational logic synthesis deals with the optimization of logic to realize a specific combinational function [2], [1]. Logic synthesis for large circuits have tremendous computing times and memory requirements. Parallel processing offers an attractive solution to this problem, hence researchers have started to investigate parallel algorithms for logic synthesis and verification [3] [4] [5]. Much of t...