A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25/spl mu/m CMOS
D. De Caro, Nicola Petra, A.G.M. Strollo · 2006
Multipartite table methods are used in the implementation of a direct digital frequency synthesizer. Two quadrature 13b outputs are produced with a SFDR >90dB and a frequency resolution of 0.15Hz at a 630MHz clock frequency. The 0.25μm CMOS chip occupies 0.063mm2and dissipates 76mW from a 2.5V supply at 630MHz