MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test
Paolo Bernardi, L. Ciganda, Ernesto Sánchez, Matteo Sonza Reorda · IEEE Transactions on Computers · 2013
Testing processor cores embedded in systems-on-chip (SoCs) is a major concern for industry nowadays. In this paper, we describe a novel solution which merges the SBST and BIST principles. The technique we propose forces the processor to execute a compact SBST-like test sequence by using a hardware module called MIcroprocessor Hardware Self-Test (MIHST) unit, which is intended to be connected to the system bus like a normal memory core, requesting no modification of the processor core internal structure. The benefit of using the MIHST approach is manifold: while guaranteeing the same or higher defect coverage of the traditional SBST approach, it reduces the time for test execution, better preserves the processor core Intellectual Property (IP), does not require the system memory to store the test program nor the test data, and can be easily adopted for non-concurrent on-line testing, since it minimizes the required system resources. The feasibility and effectiveness of the approach were evaluated on a couple of pipelined processors.