EB tester fault localization algorithm for combinational circuits by utilizing fault simulation and test pattern sequence for EB tester
Koji Nakamae, Takashi Ishimura, Hiromu Fujioka · Systems and Computers in Japan · 2000
An EB tester fault localization algorithm for combinational circuits utilizing a fault list generated in concurrent fault simulation and test pattern sequence is proposed. In the algorithm, first, an initial fault candidate list and concurrent fault lists on internal signal lines are obtained by performing concurrent fault simulation on a test pattern for which the LSI tester detected an error on one of the output pins. Then, using the concurrent fault lists, the signal line to be probed is chosen so that the fault candidate list is narrowed down maximally. One or more random test patterns are generated for a partial circuit with the probing line as an output terminal without increasing the waveform measurement time. Under the test pattern sequence composed of the fault-detected test pattern and the generated random test patterns, the EB tester probes the chosen line. Then using the probed result and the fault simulation on the added random test patterns performs the fault localization. These procedures are iterated until the number of faults included in the fault candidate list is reduced to one. The proposed algorithm was applied to eight different ISCAS'85 benchmark circuits to evaluate its performance. Results showed that the number of probed lines was reduced to about a fifth of that for the guided probed method. The increase in processing time that resulted from adopting the proposed algorithms was about 50 seconds for the circuits with several thousand gates and was less than the waveform measurement time for one probing line. Concurrent fault simulation is the main determinant of the processing time, but it is carried out only once at the initial stage. Therefore, our proposed fault localization algorithm is an efficient method relative to the guided probe method. © 2000 Scripta Technica, Syst Comp Jpn, 31(8): 41–48, 2000