Design of minimal-level PLA self-testing checkers for m-out-of-n codes
S.J. Piestrak · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1996
This paper presents the design of minimal-level PLA self-testing checkers (STCs) for incomplete m-out-of-n (m/n) codes and 1-out-of-n (1/n) codes. All checkers are selftesting for three classes of typical PLA faults and hence they are all crosspoint irredundant. A number of various incomplete m/n codes which exhibit the two-closure property with balanced partitioning are constructed, which allow one to build two-level area optimal PLA STCs for incomplete m/n codes with virtually any capacity. These new PLA STC's for m/n codes are then used to build a family of efficient three-level PLA STCs for most 1/n codes. In most cases, the new checkers offer area and/or active device number reduction, compared to existing designs which rely upon m/2m codes only. Obviously, all new minimal-level checkers can be implemented using logic gates as well.