The hardware design of effective SAO for HEVC decoder
Seungyong Park, Kwangki Ryoo · 2013
In this paper, we propose an SAO hardware architecture with less processing time, computations and reduced hardware area for a high performance HEVC decoder. The proposed SAO hardware architecture introduces the design processing 8×8 CU to reduce the hardware area and uses internal registers to support 64×64 CU processing. Instead of previous top-down block partitioning, it uses bottom-up block partitioning to minimize the amount of calculation and processing time. As a result of synthesizing the proposed architecture with TSMC 180nm library, the gate area is 30.7k and the maximum frequency is 250MHz.