Reduced Instruction Set Architecture for a GaAs Microprocessor System
Fox, Kiefer, Vangen, Whalen · Computer · 1986
Gate densities that permit the integration of an entire microprocessor on a single chip have been reached in GaAs technology. A reduced instruction set computer, or RISC, architecture is well suited to implementation in GaAs because of its low hardware requirements. The large register file and pipelined architecture typical of RISCs complement the high on-chip gate speeds of GaAs by reducing off-chip communication. In late 1984 Texas Instruments and we at Control Data, under DARPA sponsorship, began a one-year project to develop a GaAs microprocessor system with a RISC architecture. The system developed consists of a CPU, a floating-point coprocessor, or FCOP, a memory management unit, or MMU, and a cable. The streamlined architecture minimizes latencies between instructions while allowing for parallel operation between the CPU and the FCOP. The MMU manages that cache to provide a high hit rate. The tight coupling between CPU, FCOP, and MMU achieves a peak throughput of 200 MIPs.