Floating-point processors join forces in parallel processing architectures
Ray Simar, P. Koeppen, Janice Leach, Stephen D Marshall, D. Francis, Greg Mekras, J. Rosenstrauch, Shanon E. Anderson · IEEE Micro · 1992
The hardware architecture and software capabilities of the TMS320C40 floating-point digital signal processor are described. The C40 operates at 275 million operations per second (MOPS) and transfers data at a rate of 320 Mbytes/s with a 40-ns cycle time. A key architectural feature of the C40 for parallel computing is the six parallel bidirectional communication ports that permit direct connection and communication between processors in a parallel system. Examples illustrating the use of the C40 in a parallel processing environment are discussed.>