Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation
Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine · 2014
This paper investigates the effectiveness of secure dual-rail adiabatic logic against power analysis attack under CMOS process variations. The ability of the previously proposed logic in multiplier over GF(24) is investigated in terms of transitional energy dissipation using 100 data samples from Monte Carlo simulation. The adiabatic multiplier circuits are simulated using 0.18-μm and 90-nm CMOS process at an operating power clock frequency of 12.5MHz. The SPICE simulation results show that the proposed CSSAL multiplier has high stability and strong immunity in consuming constant power than other investigated logic styles.