IHARP: a multiple instruction issue processor
Gordon B. Steven, R.G. Adams, P.A. Findlay, S.A. Trainis · IEE Proceedings E Computers and Digital Techniques · 1992
Recently, multiple instruction issue architectures have attempted to improve processor performance by fetching and dispatching more than one instruction in each processor cycle. This paper describes iHARP, a multiple instruction issue processor chip, which is currently being developed at Hatfield Polytechnic. The objective of the HARP project is to develop a processor which will execute nonnumeric programs at a sustained rate in excess of two instructions per processor cycle. This paper emphasises the distinctive hardware features which have been incorporated into the iHARP chip to achieve this goal.