Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage ∗
Puneet Gupta, Andrew B. Kahng, Ion Măndoiu, Puneet Sharma · 2003
Abstract—Path delay fault testing has become increasingly important due to higher clock rates and higher process variability caused by shrinking geometries. Achieving high-coverage path delay fault testing requires the application of scan justified test vector pairs, coupled with careful ordering of the scan flip-flops and/or insertion of dummy flip-flops in the scan chain. Previous works on scan synthesis for path delay fault testing using scan shifting have focused exclusively on maximizing fault coverage and/or minimizing the number of dummy flip-flops, but have dis-regarded the scan wirelength overhead. In this paper we propose a layout-aware coverage-driven scan chain ordering method-ology and give exact and heuristic algorithms for computing the achievable tradeoffs between path delay fault coverage and both dummy flip-flop and wirelength costs. Experimental results show that our scan chain ordering methodology yields significant improvements in path delay coverage with a very small increase in wirelength overhead compared to previous layout-driven ap-proaches, and similar coverage with up to 25 times improvement in wirelength compared to previous layout-oblivious coverage-driven approaches. Index Terms—Design-for-test, physical design, scan chain syn-thesis, VLSI. I.