AProgrammable IP Core for LDPC Decoder Based onASIP
Jun Deng, Bing Li, Lintao Liu, Rui Chen · 2011
This paper proposes a programmable soft IP core of a LDPC decoder based on ASIP (application-specific instruction set processor) which can support multi-mode specified in the IEEE802.11n standard. With the presented specific microinstructions based on ASIP architecture, the decoder can process all the codes for the IEEE802.11n standard in a programmable approach, effectively, and due to the proposed 6-stage pipeline, the decoder performance is improved greatly. To verify the design, the IP has been integrated into a embedded processor system based on Xilinx EDK on a Xilinx Virtex5 FPGA component. Finally, the Logic synthesis on 0.18μm CMOS technology from UMC reveals a maximum clock frequency of 203MHz and a total area of 3.94mm2, and the corresponding power consumption is below 326.49mW.