Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern
Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun‐Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee · 2001
In this paper, an area efficient VLSI architecture of decision feedback equalizer is derived accommodating 64/256 QAM modulators. This architecture is implemented efficiently in reusable VLSI structure using EDA tool due to its regular structure. The main idea is to employ a time-multiplexed design scheme grouping the adjacent filter taps with correlated internal dataflow and with data transfer having same processing sequence between blocks. We simulated the proposed design scheme using SYNOPSYSTM and SPWTM. Index Terms - Decision feedback equalizer, QAM, reusable VLSI implementation, FIR filter.