A high performance reconfigurable parallel processing architecture
R.R. Shively, Elijah Morgan, T. W. Copley, Allen L. Gorin · 1989
The architecture of the AT&T DSP-3 parallel processor is described. The DSP-3 design is modular and when implemented with 128 processing nodes, provides a maximum throughput of 3.2 GFLOPS (32 bit floating point). The high speed interconnection network (40 Mbytes/sec) contains redundant paths that allow the machine to be configured in a variety of topologies. This flexibility supports efficient operation for a diverse set of signal processing applications and enables topology reconfiguration in support of fault tolerance. Advanced multi-chip 3-D packaging will allow a 800 MFLOP version of the machine to be realized in a multi-processor array volume of 9 cubic inches.