DAPDNA-2 Performance Enhancement Using ALU Partitioning and Saturation Arithmetic for Digital Image/Signal Processing Applications
Muhammad Ghazanfar, Shiraz Latif, Bhawani Shankar Chowdhry, A. J. Siddiqui, Ghulam Ali Mallah · 2012
A reconfigurable processor is a microprocessor with erasable hardware that can rewire itself dynamically. This allows the chip to adapt effectively to the programming tasks demanded by the particular software they are interfacing with at any given time. To modify the ALU architecture of DAPDNA-2 reconfigurable processor in order to enhance its computational capabilities for Digital Image/Signal Processing applications, we have proposed to reduce the size of ALU from 32-bit (existing) to 8, 16 or 32-bit by employing the technique of ALU Partitioning as typical DIP/DSP applications generally consist of 8 or 16-bit data types. Also, employing Saturation can help us prevent overflows as any further increment in the register values from the maximum, is supposed to be discarded for graphics applications e.g. EA2Ch + D12Ah = FFFFh.