VLSI image processor using analog programmable synapses and neurons
B.W. Lee, J.-C. Lee, B.J. Sheu · 1990
A VLSI neural network with concurrent network retrieving and learning processes is described. Weightings of analog synapse cells are externally programmed and require dynamic refreshing. Gain-adjustable neurons are used to facilitate electronic annealing to efficiently search for an optimal solution. Two prototype chips which operate in a synchronous fashion and an asynchronous fashion, respectively, were fabricated and tested. The 25-neuron chip for image restoration occupies a silicon area of 4.6×6.8 mm2in a MOSIS 2-μm CMOS process and achieves 300×speedup compared with a Sun-3/60 workstation. If implemented in industrial-level 1-μm VLSI technologies, a fully connected general-purpose neural chip with 500 neurons can be achieved in a 1-cm2silicon area