A 342mW mobile application processor with full-HD multi-standard video codec
Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori · 2009
Today's cellular phones must support full high-definition (full-HD) video in multiple video formats, such as H.264 and MPEG-2/-4, with low power consumption. Full-HD video processing requires six times the data bandwidth and is more computationally intensive than conventional standard-definition (SD) video. The trade-off between flexibility, performance and power consumption is a key focus of video-codec design. Homogeneous multi-core processors are power-consuming and achieving high-throughput is difficult [1]. While dedicated circuits can minimize power consumption, the dedicated decoders and encoders in previous reports [2, 3] have difficulty performing all of the media processing that is indispensable for a modern cellular phone [4]. In this paper, we have integrated a mobile application processor featuring a two-stage-processing video codec, tile-based address-translation circuits, and several audio/visual intellectual property (IP) modules.