An AES processing system with a compact CPU core for secure communication in embedded systems
Daisuke Tsutsumi, Isao Ohmura, Tsukasa Abe, Hitoshi Yoshimura, Kiyoshi Inagawa · 2012
Small embedded systems, such as using a 16-bit CPU, are required to connect to the Internet. In addition, the systems are required to support encrypted communication. We develop a ubiquitous platform which supports Internet Protocol version 6 (IPv6) and IP Security (IPSec). This paper describes realization of Advanced Encryption Standard (AES) processing controlled by an original compact CPU core for small embedded systems. AES encryption and decryption processing requires CPU capability. AES accelerators for a Field Programmable Gate Array (FPGA) perform high speed execution, furthermore they require the resources of an FPGA. In order to conserve the resources of the FPGA, the basic operations of AES, SubBytes, ShiftRows and MixColumns transformation, are incorporated in each hardware module. The modules are controlled by the original compact CPU core. Moreover, the CPU core is designed for small embedded systems. The CPU core is able to support only instructions used in application software. Using the CPU core, AES processing is accomplished conserving FPGA resources, and is simply designed.