A DFT method for BIST of RTL data paths based on single‐control testability
Minoru Izutsu, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara · Electronics and Communications in Japan (Part II Electronics) · 2003
Abstract In this paper, as a built‐in self‐test (BIST) scheme for register transfer level data paths, we will propose a BIST of the test per clock scheme based on hierarchical testing. In this technique, test pattern generators and response analyzers are added only to primary inputs and primary outputs of circuit under test; and for the respective combinational circuit elements, the test patterns and corresponding responses are propagated by using paths on a data path. In this paper, as a data path capable of BIST based on this hierarchical testing, we will define a single‐control testable data path, and propose a design for testability method for changing the design from a given data path to a single‐control testable data path. Moreover, the evaluation of the proposed technique is performed using benchmark circuits. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 86(2): 84–93, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/ecjb.10122