A combinatorial consideration of the error‐correcting capability of difference‐set cyclic codes
Kazumasa Kobayashi · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 1996
Abstract This paper discusses a theoretical method for estimating the error‐correcting capability (ECC) of difference‐set cyclic codes (DSCCs). DSCCs can be decoded by using majority logic decoding (MLD); however, variable threshold decoding (VTD) is often employed to improve performance. A combinatorial consideration of the ECC using MLD first must define the probability of failure to correct errors at each reference bit. Both the perfect recovery rate and the discrete probability density (DPD) of residual errors after an MLD processing are then calculated. the ECC achieved by using VTD equipped with two concatenated MLDs is estimated based on the DPD. the numerical estimations of the ECC are examined by comparing them with conventional computer simulation results. These results show that the calculated values conform well to the simulation values. the proposed method can be applied efficiently to test both error‐correcting chips and the design of the built‐in self‐test circuit for them. Results can also be applied to estimate the performances of new super‐long codes, to which little attention has been paid so far.