CRISP: a pipelined 32-bit microprocessor with 13-kbit of cache memory
Alan D. Berenbaum, Brian W. Colbry, David R. Ditzel, R.D. Freeman, Hubert R. McLellan, Kevin O’Connor, M. Shoji · IEEE Journal of Solid-State Circuits · 1987
The implementation and architecture of a 172, 163-transistor single-chip general-purpose 32-b microprocessor is described. The 16-MHz chip is fabricated using a single-metal double-poly 1.75-/spl mu/m CMOS technology and is capable of a peak execution rate of over one instruction/clock. Multiple on-chip catches, pipelining, and a one-cycle I/O protocol are utilized.