EPIC: An Architecture for Instruction-Level Parallel Processors
Michael Schlansker, B. Ramakrishna Rau · 2000
VLIW architecture, instruction-level parallelism, MultiOp, nonunit assumed latencies, NUAL, rotating register files, unbundled branches, control speculation, speculative opcodes, exception tag, predicated execution, fully-resolved predicates, wired-OR and wired-AND compare opcodes, prioritized loads and stores, data speculation, cache specifiers, precise interrupts, NUAL-freeze and NUALdrain semantics, delay buffers, replay buffers, EQ and LEQ semantics, latency stalling, MultiOp-P and MultiOp-S semantics, dynamic translation,