Overview of Applying Reachability Analysis to Verifying a Physical Microprocessor
Robert deB. Johnston, O. Dahmoune · 2011
This paper outlines the application of a Model-Checker to the functional verification of a microprocessor's physical electronic implementation. The goals are (1) testing at hardware speed, (2) reduced labor of test bench creation, and (3) a raised level of abstraction for the specifications. L. Lamport's TLC Model-Checker is used to verify a custom version of the Xilinx PicoBlaze Micro-Controller Unit (MCU), the MCU is specified in VHDL and implemented on a Field Programmable Gate Array (FPGA). Experimental verification consists of showing that the physical device behavior conforms to a mathematical specification of its Instruction Set Architecture (ISA), for selected subsets of instructions and arguments.