Implementing an MPEG2 Video Decoder Based on the TMS320C80 MVP
F. Bonomini, F. De Marco-Zompit, Gian Antonio Mian, Arnaldo Héctor Odorico, Dan Palumbo · 1998
This application report presents the preliminary results obtained in the realization of the MPEG2 video decoder on the Texas Instruments (TII) TM532OC80 MVP. We have addressed and solved the problems of bitstream scanning, variable-length code decoding, and inverse discrete cosine transform (DCT). The results obtained, integrated with preliminary work and available information about time requirements of image reconstruction for predicted and interpolated pictures, allow us to choose the architecture of the MPEG2 decoder. At present, it is possible to predict that a complete decoder will operate in real-time on one 50 MHz MVP for CCIR 601 4:2:0 sequences coded at bit-rates up to about 6 Mbit/s. This document was part of the first European DSP Education and Research Conference that took place September 26 and 27, 1996 in Paris. For information on how TI encourages students from around the world to find innovative ways to use DSPs, see TI’s World Wide Web site at www.ti.com.