Low power analysis of DLX processor datapath using a novel clocking scheme
Rajesh Kannan Megalingam, Siti Lailatul Mohd Hassan, T.Srinivasa Rao, Ashwin Mohan, V. Perieye · 2010
Low power VLSI circuit design is a core area for current research activities. Power reduction without compromising the performance is the vital concern for processor design. In this paper, we apply a new clocking scheme as in [1] that can be used to reduce the power consumption in a processor datapath. We have mainly focused on implementing the pipelined DLX processor datapath in HDL using two different clocking schemes as in [1] and analyzed the power consumption. We have adopted the method which uses dual edge triggered clock that can decrease the power consumption of a pipelined datapath considerably, without sacrificing the throughput of the CPU. Finally, we have given the experimental results which confirm the low power consumption of the DLX processor datapath.