Using the stuck-at fault model: how well does it work?
A. A. Fennisi, Douglas S. Reeves · 1990
Many researchers have studied methods for both gen erating and simulating faults in CMOS chips.A good deal of focus has been on gate level modeling and test generation methods.The stuck at fault model and various derivations of it are still most widely used to generate test sets.Other researchers have demon strated the inappropriateness of the stuck at fault model for generating effective test sets for CMOS cir cuits.Among the fault types often missed are tran sistor faults, bridging faults and delay faults.In this paper a set of experiments are described to measure the effectiveness of gate level test generation methods on transistor faults. I n t r o d u c t i o nWith the increasing densities of transistors being built onto single CMOS chips, the problem of detecting a faulty chip becomes more difficult, and the probabil ity of a faulty chip passing tests increases.Provided that the design phase of chip development is fault free, faults in a CMOS chip are the result of errors that oc cur in the fabrication process.These errors include extra or missing material on one or more of the lay ers built during fabrication.Researchers have studied the effects of these defects on circuit performance and classified them into different fault types [l]. .T h e G a t e L e v e l M o d e l a n d T e s t in gTraditionally, tests for faults in the combinational por tion of a chip have been generated using the single line (node) stuck at fault model [2].In this model, inputs and outputs of each logic gate (and, nand, inverter, etc.) are stimulated to produce the desired good out-*This work wai supported by a grant from the Microelec tronics Center of North Carolina