Low power PCM CODEC and filter system
Atsushi Iwata, K. Uchimura, S. Hattori, H. Shimizu, K. Ogasawara · IEEE Journal of Solid-State Circuits · 1981
Describes the architecture and circuit design technology for a low-power single-channel PCM CODEC and filter system. This system consists of 2 CMOS LSIs-the encoder/decoder chip using the C-R D/A conversion technique and the dual channel filter chip using the switched capacitor technique. Experimental results show how these operate with 71 mW power consumption and meet the requirements.