A chip select access time measurement method for high‐speed MOS static RAM
Yasumasa Nishimura, Koji Tanaka, Katsuki Ichinose, Takao Nakano · Electronics and Communications in Japan (Part II Electronics) · 1990
Abstract With the advance of high‐speed LSI memory devices, a longer testing time is required for accurate measurement of the access time. For accurate testing, the accuracy of the access time measurement must be improved. Although the timing accuracy of the memory tester has been improved, the accuracy of the measurement is still insufficient for testing high‐speed devices. This paper considers the chip‐select access time of the high‐speed MOS static RAM (SRAM), and proposes a method for accurate measurement using a commercial memory tester. The input signal forcing‐time to the SRAM under measurement is corrected considering the GND bounce generated by SRAM. The transmission line is terminated on the load side by the same resistance as the characteristic impedance of the transmission circuit, so that the ringing is reduced in the pulse transmission from the SRAM output terminal to the memory tester comparator. Comparing the output data with ringing suppression and the output waveform under the standard output loading, the access time select point is determined. Applying the proposed method to the commercial memory tester, the chip‐select access time is measured with the expected accuracy of 1 ns or less. To realize a further accurate measurement, several points are raised concerning the design of high‐speed MOS SRAM.