The MAJC architecture: a synthesis of parallelism and scalability
Shing Sheung Tse, A.W. Conigliam, Shailender Chaudhry, Jeremy Chan, M. Tremblay · IEEE Micro · 2000
The MAJC architecture enhances application performance by exploiting parallelism at multiple levels-instruction, data, thread, and process. Supporting vertical multithreading, speculative multithreading, and chip multiprocessors, the scalable VLIW architecture is also capable of advanced speculation and predication and treats all data types similarly.