Evaluation of range‐checking addressing modes and the architecture of FLATS2
Shûichi Ichikawa, Mitsuhisa Sato, Eiichi Goto · Systems and Computers in Japan · 1992
Abstract FLATS2 is a cyclic pipeline computer, i.e., a kind of resource‐shared MIMD computer. This paper presents the instruction set design and its realization. It is shown that efficient processings can be realized for the processings such as array processing. The result of evaluation for FLATS2 is shown and discussed. The instruction set of FLATS2 is an extension of the existing scalar instruction set. The addressing mode of FLATS2 includes the range‐checking function, as well as the function to branch according to the result of check. When the access address is within the specified range, the operation is actually executed on the memory operand and the operation branches to the specified address. If the address is outside the range, the operation does not branch but proceeds to the next instruction. If all of those operations are executed by one instruction, the array processing in the numerical calculation and symbolic processing can be made efficient. In the iterative processing by a loop, for example, the time for the loop control can be combined and concealed by superposing the loop control on the memory access and execution of operation. As a result, data are supplied continuously to the arithmetic operator and a high numerical operation performance is realized. Furthermore, it is permitted in FLATS2 to execute more than one operation by an instruction using the composite instruction, which further improves the operation performance.