A transformation for integrating VHDL behavioral specification with synthesis and software generation
Frank Vahid, Daniel D. Gajski, Sanjiv M. Narayan · European Design Automation Conference · 1994
VHDL signals and wait statements provide great ezpressiue power for behavioral specification. However, due to their climulation semantics, most high-level synthesis tools severely restrict their use, eliminating much of their power. Thus, there exists a need for a tool to bridge the gap between an arbitrary VHDL behavioral specification and existing synthesis tools. In this paper, we introduce a set of transformations to convert a VHDL description with signals and wait statements to equivalent constructs that are easily handled by high-level synthesis. The proposed transformations greatly enlarge the synthesizable VHDL subset, thus increasing the usefulness and practicality of the language as an input to high-level synthesis tools. These same transformations can also serve as a basis for converting a VHDL process to a form suitable for generation of software.