Overview of 3D NAND Flash and progress of split-page 3D vertical gate (3DVG) NAND architecture
Pei-Ying Penny Du, Hang-Ting Lue, Yen-Hao Shih, Kuang-Yeu Hsieh, Chih-Yuan Lu · 2014
This paper provides an overview of various 3D NAND Flash memory devices and a comprehensive understanding of 3DVG architectures. Compared with conventional floating gate Flash memory devices, charge-trapping (CT) devices provide much simpler 3D process integration with smaller footprint thus are naturally suitable for 3D NAND. Among various 3D NAND Flash architectures, vertical gate (VG) architecture provides superior pitch scalability and is very attractive. However, the horizontal channel makes bitline (BL) decoding more difficult so innovation is required. We proposed a split-page 3D vertical gate (3DVG) with twisted BLs (even/odd BLs in the opposite directions) that solves the decoding difficulty of VG NAND. In this work, device performance, challenges, and solutions of split-page 3DVG are addressed. Excellent MLC/TLC memory window is successfully demonstrated.